1. Field of the Invention
The invention relates to generating clock signals and synchronizing data signals with a generated clock signal. More particularly, the invention concerns processing a reference frequency signal to generate a plurality of clock signals, and synchronizing data signals with one of the generated clock signals.
2. Description of the Related Art
Code division multiple access (CDMA) cellular radiotelephone networks are a widely used type of spread spectrum communication system. Frequently, mobile telephones are small handheld units operating from battery power. Consequently, power conservation is a constant goal of handheld radiotelephone designers. A well known technique for saving power entails reducing the clock rate or completely cutting off the clock supplied to components of the radiotelephone that are not needed for the present mode of operation of the telephone. When the clock to selected components is reduced or eliminated, the telephone is in what is referred to as a secondary mode of operation.
For a CDMA radio telephone system to operate correctly, it is necessary for the radiotelephone to have a master timer that establishes and maintains synchronism with a CDMA network timer. To enable the radiotelephone to resume communications with a base station quickly and without using an excessive amount of power after leaving the secondary mode, the radiotelephone must maintain synchronism with the network timer even when the radiotelephone is in the secondary mode.
Typically, a radiotelephone has an analog transceiver that is commonly left operating when the radiotelephone is in the secondary mode, because the radiotelephone provides timing signals. However, leaving the analog transceiver operating during the secondary mode increases power consumption during the secondary mode due to the power consumption of the analog transceiver.
Consequently, there is a need for a way to maintain CDMA network time in a radiotelephone while the radiotelephone is in the secondary mode, without running the analog transceiver. Additionally, it would be desirable to clock a digital transceiver in a radiotelephone at a frequency higher than the commonly used frequency of chiprate(8), in order to allow for more efficient usage of digital transceiver resources through timesharing.
An illustrative embodiment of the invention is an integrated circuit device having a FIFO and a clock generator. The clock generator includes a pulse swallower that has an input for coupling to a reference frequency signal source, for example, from a voltage controlled temperature compensated crystal oscillator (VCTCXO). The pulse swallower eliminates pulses from the signal from the VCTCXO, producing a primary digital transceiver clock signal having a frequency of chiprate(S)(n), for example chiprate(16), at an output of the pulse swallower. The primary digital transceiver clock signal is used to clock the digital transceiver when the device is in a primary mode. An input of a first clock divider is coupled to the output of the pulse swallower. The first clock divider divides the frequency of the primary digital transceiver clock signal; to produce a FIFO output clock signal having a frequency of chiprate(S), for example chiprate(8). The output of the first clock divider is coupled to the output clock input of the FIFO. The FIFO has a data bus input for coupling to a data output, for example from an analog transceiver, providing data signals. The FIFO also has an external clock input for coupling to an output, for example from the analog transceiver, providing an external clock signal. The external clock signal is used to clock the data into the FIFO asynchronous with the primary digital transceiver clock signal at a frequency of chiprate(S), for example chiprate(8). The internal clock signal is used to clock the data out of the FIFO, synchronous with the primary digital transceiver clock signal at a frequency of chiprate (S), for example chiprate(8). Thus, the invention generates a primary digital transceiver clock signal having a frequency of chiprate(S)(n), for example chiprate(16), and synchronizes data from the analog transceiver with the generated primary digital transceiver clock signal.
Further, when in a secondary power savings mode, the pulse swallower produces an output signal having a frequency of chiprate, which is used to maintain CDMA network time without the need for any clock signals from the analog transceiver, thereby permitting the analog transceiver to be powered down during the secondary mode.
For some frequencies of the reference frequency signal, the primary digital transceiver clock signal produced at the output of the pulse swallower may have clock jitter which is too great for some applications. Consequently, in another illustrative embodiment of the invention, the external clock signal from the analog transceiver having a frequency of chiprate(S) is multiplied by (n), for example with a PLL, to produce the primary digital transceiver clock signal. As in the previously described embodiment, in this alternative embodiment, when the device is in the secondary mode, the chiprate signal for maintaining CDMA network time is generated with the external reference frequency source and the pulse swallower, allowing the analog transceiver to be powered down during the secondary mode to save power.
The invention can also be implemented as a radiotelephone and as a method. The invention advantageously provides for generation of a digital transceiver clock signal having a frequency that is higher than commonly used digital transceiver clock signals, to allow for more efficient usage of digital transceiver resources through timesharing.
The invention also provides for maintaining CDMA network time without operating the analog transceiver during the secondary mode, thereby reducing power consumption during the secondary mode. Additional advantages and benefits of the invention will be apparent from the following description.